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256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 SDRAM
DDR2 Unbuffered SDRAM MODULE
240pin Unbuffered Module based on 512Mb B-die 64/72-bit Non-ECC/ECC
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* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 Unbuffered DIMM Ordering Information
Part Number M378T3354BG(Z)3-CD5/CC M378T3354BG(Z)0-CD5/CC M378T6553BG(Z)3-CD5/CC M378T6553BG(Z)0-CD5/CC M378T2953BG(Z)3-CD5/CC M378T2953BG(Z)0-CD5/CC M391T6553BG(Z)3-CD5/CC M391T6553BG(Z)0-CD5/CC M391T2953BG(Z)3-CD5/CC M391T2953BG(Z)0-CD5/CC Density 256MB 256MB 512MB 512MB 1GB 1GB 512MB 512MB 1GB 1GB Organization 32Mx64 32Mx64 64Mx64 64Mx64 128Mx64 128Mx64 x72 ECC 64Mx72 64Mx72 128Mx72 128Mx72 64Mx8(K4T51083QB)*9 64Mx8(K4T51083QB)*9 64Mx8(K4T51083QB)*18 64Mx8(K4T51083QB)*18 Component Composition x64 Non ECC 32Mx16(K4T51163QB)*4 32Mx16(K4T51163QB)*4 64Mx8(K4T51083QB)*8 64Mx8(K4T51083QB)*8 64Mx8(K4T51083QB)*16 64Mx8(K4T51083QB)*16
DDR2 SDRAM
Number of Rank 1 1 1 1 2 2 1 1 2 2 Height 30mm 30mm 30mm 30mm 30mm 30mm 30mm 30mm 30mm 30mm
Note: "Z" of Part number(11th digit) stand for Lead-free products. Note: "3" of Part number(12th digit) stand for Dummy Pad PCB products.
Features
* Performance range
D5(DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 533 4-4-4 CC(DDR2-400) 400 400 3-3-3 Unit Mbps Mbps Mbps CK
* JEDEC standard 1.8V 0.1V Power Supply * VDDQ = 1.8V 0.1V * 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin * 4 Banks * Posted CAS * Programmable CAS Latency: 3, 4, 5 * Programmable Additive Latency: 0, 1 , 2 , 3 and 4 * Write Latency(WL) = Read Latency(RL) -1 * Burst Length: 4 , 8(Interleave/nibble sequential) * Programmable Sequential / Interleave Burst Mode * Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) * Off-Chip Driver(OCD) Impedance Adjustment * On Die Termination * Average Refresh Period 7.8us at lower than a TCASE 85C, 3.9us at 85C < TCASE < 95 C - support High Temperature Self-Refresh rate enable feature * Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16 * All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung's Device operation & Timing diagram.
Address Configuration
Organization
64Mx8(512Mb) based Module 32Mx16(512Mb) based Module
Row Address
A0-A13 A0-A12
Column Address
A0-A9 A0-A9
Bank Address
BA0-BA1 BA0-BA1
Auto Precharge
A10 A10
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
x64 DIMM Pin Configurations (Front side/Back side)
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DDR2 SDRAM
Front
A4 VDDQ A2 VDD KEY VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ S1 ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41
Front
VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18
Pin
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Back
VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 CK1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23
Pin
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Front
DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS NC NC VSS NC NC VSS NC NC VSS VDDQ CKE0 VDD NC NC VDDQ A11 A7 VDD A5
Pin
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Back
VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS NC NC VSS NC NC VSS NC NC VSS VDDQ CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6
Pin
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
Pin
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
Back
VDDQ A3 A1 VDD CK0 CK0 VDD A0 VDD BA1 VDDQ RAS S0 VDDQ ODT0 A131 VDD VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS
Pin
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Front
VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC, TEST2 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL
Pin
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Back
DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 CK2 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
NC = No Connect, RFU = Reserved for Future Use 1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
x72 DIMM Pin Configurations (Front side/Back side)
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DDR2 SDRAM
Front
A4 VDDQ A2 VDD KEY VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ S1 ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41
Front
VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18
Pin
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Back
VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 CK1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23
Pin
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Front
DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD NC NC VDDQ A11 A7 VDD A5
Pin
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Back
VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS VDDQ CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6
Pin
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
Pin
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
Back
VDDQ A3 A1 VDD CK0 CK0 VDD A0 VDD BA1 VDDQ RAS S0 VDDQ ODT0 A13 VDD VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS
Pin
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Front
VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC, TEST2 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL
Pin
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Back
DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 CK2 VSS DM6 NC VSS DQ54 DQ55 VSS
DQ60 DQ61 VSS DM7 NC
VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
NC = No Connect, RFU = Reserved for Future Use 1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Pin Description
Pin Name A0-A13 BA0, BA1 RAS CAS WE S0, S1 CKE0,CKE1 ODT0, ODT1 DQ0 - DQ63 CB0 - CB7 DQS0 - DQS8 DM(0-8) DQS0-DQS8 Description DDR2 SDRAM address bus DDR2 SDRAM bank select DDR2 SDRAM row address strobe DDR2 SDRAM column address strobe DDR2 SDRAM wirte enable DIMM Rank Select Lines DDR2 SDRAM clock enable lines On-die termination control lines DIMM memory data bus DIMM ECC check bits DDR2 SDRAM data strobes DDR2 SDRAM data masks DDR2 SDRAM differential data strobes Pin Name CK0, CK1, CK2 CK0, CK1, CK2 SCL SDA SA0-SA2 VDD* VDDQ* VREF VSS VDDSPD NC RESET TEST Description DDR2 SDRAM clocks (positive line of differential pair) DDR2 SDRAM clocks (negative line of differential pair) I2C serial bus clock for EEPROM I2C serial bus data line for EEPROM I2C serial address select for EEPROM DDR2 SDRAM core power supply DDR2 SDRAM I/O Driver power supply DDR2 SDRAM I/O reference supply Power supply return (ground) Serial EEPROM positive power supply Spare Pins(no connect) Not used on UDIMM Used by memory bus analysis tools (unused on memory DIMMs)
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
Input/Output Functional Description
Symbol CK0-CK2 CK0-CK2 CKE0-CKE1 S0-S1 RAS, CAS, WE ODT0-ODT1 VREF VDDQ BA0-BA1 Type Input Input Input Input Input Supply Supply Input Function
DDR2 SDRAM
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing) Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disbled, new command are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks RAS, CAS, and WE (ALONG WITH CS) define the command being entered. When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the Extended Mode Register Set (EMRS). Reference voltage for SSTL 18 inputs. Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. Selects which SDRAM BANK of four is activated. During a Bank Activate command cycle, Address input defines the row address (RA0-RA13) During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to precharge. Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM These signals and tied at the system planar to either VSS or VDD to configure the serial SPD EERPOM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pullup on the system board. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pullup onthe system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V.
A0-A13
Input
DQ0-DQ63 CB0-CB7 DM0-DM8
In/Out
Input
VDD,VSS DQS0-DQS8 DQS0-DQS8 SA0-SA2 SDA SCL VDD SPD
Supply In/Out Input In/Out Input Supply
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 512MB, 64Mx64 Module(Populated as 1 rank of x8 DDR2 SDRAMs) M378T6553BG(Z)3 / M378T6553BG(Z)0
S0 DQS0 DQS0 DM0
DM CS DQS DQS
DQS4 DQS4 DM4
DM CS DQS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DM2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
DM
NU/ CS
DQS DQS
DM
CS
DQS DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
Serial PD SCL WP A0 SA0 BA0 - BA1 A0 - A13 RAS CAS CKE0 WE ODT0 A1 SA1 A2 SA2 SDA
VDDSPD VDD/VDDQ VREF VSS
Serial PD D0 - D7 D0 - D7 D0 - D7
* Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 2 DDR2 SDRAMs *CK1/CK1 3 DDR2 SDRAMs *CK2/CK2 3 DDR2 SDRAMs
*Wire per Clock Loading Table/Wiring Diagrams
BA0-BA1 : DDR2 SDRAMs D0 - D7 A0-A13 : DDR2 SDRAMs D0 - D7 RAS : DDR2 SDRAMs D0 - D7 CAS : DDR2 SDRAMs D0 - D7 CKE : DDR2 SDRAMs D0 - D7 WE : DDR2 SDRAMs D0 - D7 ODT : DDR2 SDRAMs D0 - D7
Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms 5%.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 512MB, 64Mx72 ECC Module(Populated as 1 rank of x8 DDR2 SDRAMs) M391T6553BG(Z)3 / M391T6553BG(Z)0
S0 DQS0 DQS0 DM0
DM CS DQS DQS
DQS4 DQS4 DM4
DM CS DQS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DM2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM8
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
Serial PD
DM CS DQS DQS
SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D8
VDDSPD VDD/VDDQ
Serial PD D0 - D8 D0 - D8 D0 - D8
* Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 3 DDR2 SDRAMs *CK1/CK1 3 DDR2 SDRAMs *CK2/CK2 3 DDR2 SDRAMs
*Wire per Clock Loading Table/Wiring Diagrams
BA0 - BA1 A0 - A13 RAS CAS CKE0 WE ODT0
BA0-BA1 : DDR2 SDRAMs D0 - D8 A0-A13 : DDR2 SDRAMs D0 - D8 RAS : DDR2 SDRAMs D0 - D8 CAS : DDR2 SDRAMs D0 - D8 CKE : DDR2 SDRAMs D0 - D8 WE : DDR2 SDRAMs D0 - D8 ODT : DDR2 SDRAMs D0 - D8
VREF VSS
Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms 5%.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs) M378T2953BG(Z)3 / M378T2953BG(Z)0
S1 S0 DQS0 DQS0 DM0
DM CS DQS DQS DM CS DQS DQS
DQS4 DQS4 DM4
DM CS DQS DQS DM CS DQS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D8
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D12
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DM2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D9
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D13
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D10
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D14
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D11
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D15
VDDSPD VDD/VDDQ VREF VSS
Serial PD D0 - D15 D0 - D15 D0 - D15
Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
* Clock Wiring Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 DDR2 SDRAMs 4 DDR2 SDRAMs 6 DDR2 SDRAMs 6 DDR2 SDRAMs
BA0 - BA1 A0 - A13 CKE0 CKE1 RAS CAS WE ODT0 ODT1
BA0-BA1 : DDR2 SDRAMs D0 - D15 A0-A13 : DDR2 SDRAMs D0 - D15 CKE : DDR2 SDRAMs D0 - D7 CKE : DDR2 SDRAMs D8 - D15 RAS : DDR2 SDRAMs D0 - D15 CAS : DDR2 SDRAMs D0 - D15 WE : DDR2 SDRAMs D0 - D15 ODT : DDR2 SDRAMs D0 - D7 ODT : DDR2 SDRAMs D8 - D15
*Wire per Clock Loading Table/Wiring Diagrams Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms 5%.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx72 ECC Module(Populated as 2 ranks of x8 DDR2 SDRAMs) M391T2953BG(Z)3 / M391T2953BG(Z)0
S1 S0 DQS0 DQS0 DM0
DM CS DQS DQS DM CS DQS DQS
DQS4 DQS4 DM4
DM CS DQS DQS DM CS DQS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D9
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D13
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DM2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D10
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D14
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D11
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D15
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM8
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D12
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D16
Serial PD
DM CS DQS DQS DM CS DQS DQS
SCL WP SDA A0 SA0 A1 SA1 A2 SA2
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D8
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D17
* Clock Wiring Clock Input
VDDSPD VDD/VDDQ VREF VSS Serial PD D0 - D17 D0 - D17 D0 - D17
DDR2 SDRAMs 6 DDR2 SDRAMs 6 DDR2 SDRAMs 6 DDR2 SDRAMs
BA0 - BA1 A0 - A13 CKE0 CKE1 RAS CAS WE ODT0 ODT1
BA0-BA1 : DDR2 SDRAMs D0 - D17 A0-A13 : DDR2 SDRAMs D0 - D17 CKE : DDR2 SDRAMs D0 - D8 CKE : DDR2 SDRAMs D9 - D17 RAS : DDR2 SDRAMs D0 - D17 CAS : DDR2 SDRAMs D0 - D17 WE : DDR2 SDRAMs D0 - D17 ODT : DDR2 SDRAMs D0 - D8 ODT : DDR2 SDRAMs D9 - D17
*CK0/CK0 *CK1/CK1 *CK2/CK2
*Wire per Clock Loading Table/Wiring Diagrams
Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms 5%.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 256MB, 32Mx64 Module(Populated as 1 rank of x16 DDR2 SDRAMs) M378T3354BG(Z)3 / M378T3354BG(Z)0
S0
CS CS
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
LDQS LDOS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDOS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
DQS5 DQS5 DM5
D0
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS4 DQS4 DM4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
LDQS LDOS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDOS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
D2
CS
CS
DQS3 DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS2 DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
LDQS LDOS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDOS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
DQS7 DQS7 DM7
D1
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS6 DQS6 DM6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
LDQS LDOS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDOS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
D3
VDDSPD
Serial PD D0 - D3 D0 - D3 D0 - D3
* Clock Wiring Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 DDR2 SDRAMs NC 2 DDR2 SDRAMs 2 DDR2 SDRAMs
Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
VDD/VDDQ VREF VSS
*Wire per Clock Loading Table/Wiring Diagrams
BA0 - BA1 A0 - A12 CKE0 RAS CAS WE ODT0
BA0-BA1 : DDR2 SDRAMs D0 - D3 A0-A12 : DDR2 SDRAMs D0 - D3 CKE : DDR2 SDRAMs D0 - D3 RAS : DDR2 SDRAMs D0 - D3 CAS : DDR2 SDRAMs D0 - D3 WE : DDR2 SDRAMs D0 - D3 ODT : DDR2 SDRAMs D0 - D3 Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms 5%. 4. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms 5%.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
Absolute Maximum DC Ratings
Symbol VDD VDDQ VDDL VIN, VOUT TSTG Parameter Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Rating - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100
DDR2 SDRAM
Units V V V V C Notes 1 1 1 1 1, 2
Note : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Symbol VDD VDDL VDDQ VREF VTT Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V 4 4 1,2 3 Notes
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
Operating Temperature Condition
Symbol TOPER Parameter Operating Temperature Rating 0 to 95 Units C
DDR2 SDRAM
Notes 1, 2, 3
Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 0 - 85 C, operation temperature range are the temperature which all DRAM specification will be supported. 3. At 85 - 95 C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol VIH(DC) VIL(DC) Parameter DC input logic high DC input logic low Min. VREF + 0.125 - 0.3 Max. VDDQ + 0.3 VREF - 0.125 Units V V Notes
Input AC Logic Level
Symbol VIH(AC) VIL(AC) Parameter AC input logic high AC input logic low Min. VREF + 0.250 Max. VREF - 0.250 Units V V Notes
AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Condition Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VDDQ VIH(AC) min VSWING(MAX) VIH(DC) min VREF VIL(DC) max VIL(AC) max delta TF Falling Slew = VREF - VIL(AC) max delta TF delta TR Rising Slew = VSS VIH(AC) min - VREF delta TR
< AC Input Test Signal Waveform >
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol IDD0 Proposed Conditions
DDR2 SDRAM
Units mA
Notes
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0mA Slow PDN Exit MRS(12) = 1mA
IDD1
mA
IDD2P
mA
IDD2Q
mA
IDD2N
mA mA mA mA
IDD3P
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal Low Power
IDD4W
mA
IDD4R
mA
IDD5B
mA mA mA
IDD6
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions
mA
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)
M378T6553BG(Z)3 / M378T6553BG(Z)0 : 512MB(64Mx8 *8) Module
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 Normal
DDR2 SDRAM
D5 (DDR2-533@CL=4)
800 880 64 200 240 240 120 560 1,600 1,440 1,560 44 2,200
CC (DDR2-400@CL=3)
760 800 64 200 240 240 120 520 1,160 1,160 1,480 44 2,160
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M378T2953BG(Z)3 / M378T2953BG(Z)0 : 1GB(64Mx8 *16) Module
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 Normal
D5 (DDR2-533@CL=4)
1,360 1,440 128 400 480 480 240 1,120 2,160 2,000 2,120 88 2,760
CC (DDR2-400@CL=3)
1,280 1,320 128 400 480 480 240 1,040 1,680 1,680 2,000 88 2,680
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)
M378T3354BG(Z)3 / M378T3354BG(Z)0 : 256MB(32Mx16 *4) Module
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 Normal
DDR2 SDRAM
D5 (DDR2-533@CL=4)
480 580 32 100 120 120 60 280 920 820 780 22 1,560
CC (DDR2-400@CL=3)
460 500 32 100 120 120 60 260 740 680 740 22 1,500
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M391T6553BG(Z)3 / M391T6553BG(Z)0 : 512MB(64Mx8 *9) ECC Module
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 Normal
D5 (DDR2-533@CL=4)
900 990 72 225 270 270 135 630 1,800 1,620 1,755 50 2,475
CC (DDR2-400@CL=3)
855 900 72 225 270 270 135 585 1,305 1,305 1,665 50 2,430
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
Operating Current Table(1-3) (TA=0oC, VDD= 1.9V)
M391T2953BG(Z)3 / M391T2953BG(Z)0 : 1GB(64Mx8 *18) ECC Module
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 Normal
DDR2 SDRAM
D5 (DDR2-533@CL=4)
1,530 1,620 144 450 540 540 270 1,260 2,430 2,250 2,385 99 3,105
CC (DDR2-400@CL=3)
1,440 1,485 144 450 540 540 270 1,170 1,890 1,890 2,250 99 3,015
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Input/Output Capacitance (VDD=1.8V, VDDQ=1.8V, TA=25oC)
Parameter Non-ECC Symbol Min Max Min Max Min Max Units M378T6553BG(Z)3 M378T6553BG(Z)0 24 25 25 42 42 6 M378T2953BG(Z)3 M378T2953BG(Z)0 26 28 28 42 42 10 M378T3354BG(Z)3 M378T3354BG(Z)0 22 24 24 34 34 6 Units pF
CCK0 Input capacitance, CK and CK CCK1 CCK2 Input capacitance, CKE and CS Input capacitance, Addr, RAS, CAS, WE Input/output capacitance, DQ, DM, DQS, DQS ECC CI1 CI2 CIO Symbol CCK0 Input capacitance, CK and CK CCK1 CCK2 Input capacitance, CKE and CS Input capacitance, Addr, RAS, CAS, WE Input/output capacitance, DQ, DM, DQS, DQS CI1 CI2 CIO
M391T6553BG(Z)3 M391T6553BG(Z)0 25 25 25 44 44 6
M391T2953BG(Z)3 M391T2953BG(Z)0 28 28 28 44 44 10
pF
* DM is internally loaded to match DQ and DQS identically.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(0 C < TCASE < 95 C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
DDR2 SDRAM
Refresh Parameters by Device Density
Parameter Refresh to active/Refresh command time Average periodic refresh interval tRFC tREFI 0 C TCASE 85C 85 C < TCASE 95C Symbol 256Mb 75 7.8 3.9 512Mb 105 7.8 3.9 1Gb 127.5 7.8 3.9 2Gb 195 7.8 3.9 4Gb tbd 7.8 3.9 Units ns s s
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed Bin (CL - tRCD - tRP) Parameter tCK, CL=3 tCK, CL=4 tCK, CL=5 tRCD tRP tRC tRAS min 5 3.75 15 15 55 40 70000 DDR2-533(D5) 4-4-4 max 8 8 min 5 5 15 15 55 40 70000 DDR2-400(CC) 3-3-3 max 8 8 ns ns ns ns ns ns ns Units
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input hold time DQ and DM input setup time Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time
DQS falling edge hold time from CK
Symbol
tAC tDQSCK tCH tCL tHP tCK tDH tDS tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD
DDR2-533 min
-500 -450 0.45 0.45 min(tCL, tCH) 3750 225 100 0.6 0.35 x tAC min 2* tACmin x x tHP - tQHS WL-0.25 0.35 0.35 0.2 0.2 2
DDR2-400 min
-600 -500 0.45 0.45 min(tCL, tCH) 5000 275 150 0.6 0.35 x tAC min 2* tACmin x x tHP - tQHS WL-0.25 0.35 0.35 0.2 0.2 2
Units
ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK
Notes
max
+500 +450 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 300 400 x WL+0.25 x x x x x
max
+600 +500 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 350 450 x WL+0.25 x x x x x
20,21 24 15,16,17 15,16,17
Mode register set command cycle time
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
Parameter
Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size products Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW
DDR2 SDRAM
DDR2-533 DDR2-400 min
0.4 0.35 475 350 0.9 0.4 7.5 10 37.5 50 2 x x x 15 tWR+tRP 10 7.5 tRFC + 10 200 x x 2 2 6 - AL x x x x x
Symbol
tWPST tWPRE tIH tIS tRPRE tRPST tRRD tRRD tFAW tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS
t
Units
0.6 x x x 1.1 0.6 x x tCK tCK ps ps tCK tCK ns ns ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK 2 tCK ns ns tCK ns ns tCK tCK 12 ns ns
Notes
min
0.4 0.35 375 250 0.9 0.4 7.5 10 37.5 50 2 15 tWR+tRP 7.5 7.5 tRFC + 10 200 2 2 6 - AL
max
0.6 x x x 1.1 0.6 x x
max
CKE
3
2 tAC(min) tAC(min)+2 2.5
tAC(min)
3
2 tAC(max)+1 2tCK+tAC(m ax)+1 2.5
tAC(max)+ 0.6
tAOND t
2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8
AON
tAC(max)+1 2tCK+tAC (max)+1 2.5
tAC(max)+ 0.6
tAONPD t
AOFD
tAOF t
AOFPD
tAC(min)+2 3 8 0 tIS+tCK +tIH
2.5tCK+ tAC(max)+1
2.5tCK+ tAC(max)+1
tANPD tAXPD tOIT tDelay
12
0 tIS+tCK +tIH
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
Physical Dimensions: 64Mbx8 based 64Mx64/x72 Module(1 Rank) M378T6553BG(Z)3 / M391T6553BG(Z)3 M378T6553BG(Z)0 / M391T6553BG(Z)0
133.35 131.35 128.95 (2X)4.00
DDR2 SDRAM
Units : Millimeters
10.00
(for x64) (for x72)
N/A
ECC
SPD
30.00
2.30
(2) 2.50
A 63.00
B 55.00 2.7
1.270 0.10
5.00 4.00
4.00
2.500.20
3.00 0.800.05
3.80
0.20 4.00
2.50
1.500.10
1.00
Detail A
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QB
Rev. 1.5 Aug. 2005
17.80
256MB, 512MB, 1GB Unbuffered DIMMs
Physical Dimensions: 64Mbx8 based 128Mx64/x72 Module(2 Ranks) M378T2953BG(Z)3 / M391T2953BG(Z)3 M378T2953BG(Z)0 / M391T2953BG(Z)0
133.35 131.35 128.95 (2X)4.00
DDR2 SDRAM
Units : Millimeters
10.00
(for x64) (for x72)
N/A
SPD
ECC
30.00
2.30
(2) 2.50
A 63.00
B 55.00 4.00
(for x64) (for x72)
N/A
ECC
5.00 4.00
4.00
2.500.20
3.00 0.800.05
3.80
0.20 4.00
2.50
1.500.10
1.00
Detail A
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QB
Rev. 1.5 Aug. 2005
17.80 1.270 0.10
256MB, 512MB, 1GB Unbuffered DIMMs
Physical Dimensions: 32Mbx16 based 32Mx64 Module(1 Rank) M378T3354BG(Z)3 / M378T3354BG(Z)0
DDR2 SDRAM
Units : Millimeters
133.35 131.35 128.95 (2X)4.00
SPD
10.00
30.00
2.30
(2) 2.50
A 63.00
B 55.00 2.7
5.00 4.00
4.00
2.500.20
3.00 0.800.05
3.80
0.20 4.00
2.50
1.500.10
1.00
Detail A
Detail B
The used device is 32M x16 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51163QB
Rev. 1.5 Aug. 2005
17.80 1.270 0.10
256MB, 512MB, 1GB Unbuffered DIMMs
Revision History
Revision 1.0 (Jan. 2004)
- Initial Release
DDR2 SDRAM
Revision 1.1 (Jun. 2004)
- Added lead-free part number in the ordering information - Changed IDD2P
Revision 1.2 (Jul. 2004)
- Added current values and part number of low power product
Revision 1.3 (Feb. 2005)
- Added the detail information for mechanical dimension
Revision 1.4 (Mar. 2005)
- Changed 1GB Functional Block Diagram
Revision 1.5 (Aug. 2005)
- Added Dummy Pad PCB product part number in the ordering information
Rev. 1.5 Aug. 2005

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